1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to a method of manufacture of vertical channel flash memory devices.
2. Description of Related Art
1. To maintain enough current through channel regions conventional memory cells require more chip surface area with traditional ETOX (nonvolatile memory with a metal drain line that contacts each drain region in a column of drain regions) structures since the channel is parallel to the wafer surface. PA0 2. Field oxide regions are used to provide isolation for conventional ETOX structure requiring space between memory cells. PA0 3. During programming and erasing procedures, the tunneling electrons always.need to pass through part of the channel area resulting in charge trapping and transconductance degradation. PA0 1. A cell structure in accordance with this invention uses a vertical channel but not the traditional horizontal one. PA0 2. A cell structure in accordance with this invention can be packed more densely for a cell array since the channel is vertical with respect to the wafer surface. PA0 3. The P/N junction is used for isolation instead of a field oxide layer at the reverse bias for the P/N junction. PA0 4. The stacked gate structure is planarized in accordance with this invention. PA0 5. During the erasing procedure, the band-to-band hot hole phenomenon can be completely prevented with a cell structure in accordance with this invention. PA0 1. The unit cell can take requires less surface area but provides an enlarged channel area. PA0 2. Because the floating gate is under the wafer surface and because no field oxide is employed, the stacking gate is planarized. In addition, the step height of the stacked gate is the same as that of peripheral devices. Thus, only one mask is necessary to conduct both the stacked gate and the control gate etching instead of two masks for a conventional ETOX structure. PA0 3. The tunnel oxide, which is used for erasing, is between the source/drain regions and the floating gate and does not overlap with the channel. Therefore, the band-to-band hot hole phenomenon can be completely prevented during the erasing procedure since the conventional P/N junction formed from the source/drain region with the bulk region is not involved in this cell structure. PA0 4. Since the portion of the tunnel oxide layer used for erasing is not located in the channel, the window close behavior coming from erasing can be avoided. PA0 5. Because the area of the tunnel oxide layer between the source/drain and floating gate is much larger than that of the traditional structure, it can be expected that the erasing speed will be much faster also.
See the references as follows:
U.S. Pat. No. 5,045,490 of Esquivel et al. for "Method of Making a Pleated Floating Gate Trench EPROM"; PA1 U.S. Pat. No. 5,595,927 of Chen et al. for "Method for Making Self-Aligned Source/Drain Mask ROM Memory Cell Using Trench Etched Channel"; and PA1 U.S. Pat. No. 5,563,083 of Pein for "Method of Fabricating Non-Volatile Sidewall Memory Cell".